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document no. e0195e30 (ver. 3.0) date published june 2002 (k) japan url: http:// www.elpida.com ? elpida memory, inc. 2001-2002 data sheet 128m bits mobile ram edl1216casa (8m words 16 bits) description the edl1216ca is a 128m bits mobile ram organized as 2 ,097,152 words 16 bits 4 banks. the mobile ram achieved low power consumption and high-speed data transfer using the pipeline architecture. all inputs and outputs are synchronized with the positive edge of the clock. this product is packaged in 54-ball fbga ( bga ? ). features ? low voltage power supply ? vdd: 1.8v 0.15v ? vddq: 1.8v 0.15v ? wide temperature range ( ? 25 c to 85 c) ? programmable partial self refresh ? programmable driver strength ? programmable temperature compensated self refresh (option) ? deep power down mode ? small package (54-ball fbga ( bga)) ? fully synchronous dynamic ram, with all signals referenced to a positive clock edge ? pulsed interface ? possible to assert random column address in every cycle ? quad internal banks controlled by ba0 and ba1 ? byte control by ldqm and udqm ? wrap sequence = sequential/ interleave ? /cas latency (cl) = 2, 3 ? automatic precharge and controlled precharge ? auto refresh and self refresh ? 16 organization ? 4,096 refresh cycles/64ms ? burst termination by burst stop command and precharge command ? fbga( bga) package is lead free solder (sn-ag-cu) applications mobile cellular handsets, pdas, wireless pdas, handheld p c s , home electronic appliances, and information appliances, etc. pin configurations /xxx indicates active low si gnal. vss 1 a b c d e f g h j 23456789 dq14 dq12 dq10 dq8 udqm nc a8 vss dq15 dq13 dq11 dq9 nc clk a11 a7 a5 vssq vddq vssq vddq vss cke a9 a6 a4 vddq vssq vddq vssq vdd /cas ba0 a0 a3 dq0 dq2 dq4 dq6 ldqm /ras ba1 a1 a2 vdd dq1 dq3 dq5 dq7 /we /cs a10 vdd (top view) a0 to a11 address inputs ba0, ba1 bank select dq0 to dq15 data inputs/ outputs clk clock input cke clock enable /cs chip select /ras row address strobe /cas column address strobe /we write enable udqm upper dq mask enable ldqm lower dq mask enable vdd power supply vss ground vddq power supply for dq vssq ground for dq nc no connection 54-ball fbga ( bga)
edl1216casa data sheet e0195e30 (ver. 3.0) 2 ordering information part number organization (words bits) internal banks clock frequency mhz (max.) /cas latency package EDL1216CASA-10-E 8m 16 4 100 3 54-ball fbga ( bga) part number lead free elpida memory density / bank 12: 128m /4 banks bit organization 16: x16 voltage, interface c: vdd = 1.8v, vddq = 1.8v, lvcmos die rev. package sa: bga speed 10: 100mhz product code l: mobile ram type d: monolithic device e d l 12 16 c a sa - 10 - e
edl1216casa data sheet e0195e30 (ver. 3.0) 3 contents description .................................................................................................................... ................................ 1 features ....................................................................................................................... ................................. 1 applications ................................................................................................................... ................................ 1 pin configurations ............................................................................................................. ............................ 1 ordering information ........................................................................................................... .......................... 2 electrical specifications...................................................................................................... ........................... 4 pin function ................................................................................................................... ............................... 9 command operation .............................................................................................................. ..................... 10 truth table .................................................................................................................... .............................. 14 simplified state diagram....................................................................................................... ...................... 19 initialization................................................................................................................. ................................. 20 programming mode registers ..................................................................................................... ............... 20 address bits of bank-select and precharge ...................................................................................... ......... 24 operation of the mobile ram.................................................................................................... .................. 25 timing waveforms ............................................................................................................... ....................... 33 package drawing ................................................................................................................ ........................ 56 recommended soldering conditions............................................................................................... ........... 57 revision history ............................................................................................................... ........................... 60
edl1216casa data sheet e0195e30 (ver. 3.0) 4 electrical specifications ? all voltages are referenced to vss (gnd). ? after power up, wait more than 200 s and then, execute power on sequence and two auto refresh before proper device operation is achieved. absolute maximum ratings parameter symbol rating unit note voltage on any pin relative to vss vt C0.5 to +3.6 v supply voltage relative to vss vdd, vddq C0.5 to +2.6 v short circuit output current ios 50 ma power dissipation pd 1.0 w operating ambient temperature ta C25 to +85 c storage temperature tstg C55 to +125 c caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions (ta = C25 to +85 c) parameter symbol min. typ. max. unit notes supply voltage vdd 1.65 1.8 1.95 v vss 0 0 0 v dq supply voltage vddq 1.65 1.8 1.95 v input high voltage vih 0.8 vddq ? vddq + 0.3* 1 v input low voltage vil C0.3* 2 ? 0.3 v notes: 1. vih (max.) = vddq + 1.5v (pulse width 5ns). 2. vil (min.) = C1.5v (pulse width 5ns).
edl1216casa data sheet e0195e30 (ver. 3.0) 5 dc characteristics 1 (ta = C25 to +85 c, vdd, vddq = 1.8v 0.15v, vss, vssq = 0v) parameter /cas latency symbol grade max. unit test condition notes operating current (cl = 2) idd1 60 ma 1 (cl = 3) idd1 60 ma burst length = 1 trc trc min., io = 0ma, one bank active standby current in power down idd2p 0.9 ma cke vil max., tck = 15ns standby current in power down (input signal stable) idd2ps 0.5 ma cke vil max., tck = standby current in non power down idd2n 5.5 ma cke vih min., tck = 15ns, /cs vih min., input signals are changed one time during 30ns. standby current in non power down (input signal stable) idd2ns 2 ma cke vih min., tck = , input signals are stable. active standby current in power down idd3p 1.5 ma cke vil max., tck = 15ns active standby current in power down (input signal stable) idd3ps 1 ma cke vil max., tck = active standby current in non power down idd3n 17 ma cke vih min., tck = 15 ns, /cs vih min., input signals are changed one time during 30ns. active standby current in non power down (input signal stable) idd3ns 12 ma cke vih min., tck = , input signals are stable. burst operating current (cl = 2) idd4 40 ma tck tck min., iout = 0ma, all banks active 2 (cl = 3) idd4 60 ma refresh current (cl = 2) idd5 130 ma trc trc min. 3 (cl = 3) idd5 130 ma self refresh current pasr="000" (full) idd6 0.35 ma tcsr="00" (ts* 4 70c) pasr="001" (2bk) 0.25 ma cke 0.2v pasr="010" (1bk) 0.18 ma pasr="101" (1/2 bk) 0.12 ma pasr="110" (1/4 bk) 0.09 ma pasr="000" (full) idd6 0.20 ma tcsr="01" (ts* 4 45c) pasr="001" (2bk) 0.15 ma cke 0.2v pasr="010" (1bk) 0.10 ma pasr="101" (1/2 bk) 0.08 ma pasr="110" (1/4 bk) 0.07 ma pasr="000" (full) idd6 0.60 ma tcsr="11" (ts* 4 85c) pasr="001" (2bk) 0.50 ma cke 0.2v pasr="010" (1bk) 0.43 ma pasr="101" (1/2 bk) 0.37 ma pasr="110" (1/4 bk) 0.34 ma standby current in deep power down mode idd7 10 a cke 0.2v
edl1216casa data sheet e0195e30 (ver. 3.0) 6 notes: 1. idd1 depends on output loading and cycle rates. specified values are obtained with the output open. in addition to this, idd1 is measured condition that addresses are changed only one time during tck (min.). 2. idd4 depends on output loading and cycle rates. specified values are obtained with the output open. in addition to this, idd4 is measured condition that addresses are changed only one time during tck (min.). 3. idd5 is measured on condition that addresses are changed only one time during tck (min.). 4. ts is surface temperature. dc characteristics 2 (ta = C25 to +85 c, vdd, vddq = 1.8v 0.15v, vss, vssq = 0v) parameter symbol min. max. unit test condition notes input leakage current ili C1.0 1.0 a 0 vin vddq output leakage current ilo C1.5 1.5 a 0 vout vddq, dq = disable output high voltage voh vddq C 0.2 v ioh = C0.1 ma output low voltage vol 0.2 v iol = 0.1 ma pin capacitance (ta = 25c, f = 1mhz) parameter symbol pins min. typ max. unit notes input capacitance ci1 clk 2.0 3.5 pf ci2 address, cke, /cs, /ras, /cas, /we, udqm, ldqm 2.0 3.8 pf data input/output capacitance ci/o dq 4 6.5 pf
edl1216casa data sheet e0195e30 (ver. 3.0) 7 ac characteristics (ta = C25 to +85 c, vdd, vddq = 1.8v 0.15v, vss, vssq = 0v) test conditions ? ac high level input voltage / low level input voltage: 1.6 / 0.2v ? input timing measurement reference level: 0.9v ? transition time (input rise and fall time): 1ns ? output timing measurement reference level: 0.9v hz h h; 86kk a6fk a6gk h;z 86kk a6fk a6gk <+> ?;C =h
edl1216casa data sheet e0195e30 (ver. 3.0) 8 synchronous characteristics parameter symbol min. max. unit note clock cycle time (cl= 2) tck2 15 ns (cl= 3) tck3 10 ns access time from clk (cl= 2) tac2 7 ns 1 (cl= 3) tac3 6 ns 1 clk high level width tch 3 ns clk low level width tcl 3 ns data-out hold time toh 3 ns 1 data-out low-impedance time tlz 0 ns data-out high-impedance time (cl= 2) thz2 3 7 ns (cl= 3) thz3 3 6 ns data-in setup time tds 2 ns data-in hold time tdh 1 ns address setup time tas 2 ns address hold time tah 1 ns cke setup time tcks 2 ns cke hold time tckh 1 ns cke setup time (power down exit) tcksp 2 ns command (/cs, /ras, /cas, /we, udqm, ldqm) setup time tcms 2 ns command (/cs, /ras, /cas, /we, udqm, ldqm) hold time tcmh 1 ns note: 1. output load. kwk4a k ? output load asynchronous characteristics parameter symbol min. max. unit notes act to ref/act command period (operation) trc 90 ? ns act to ref/act command period (refresh) trc1 90 ? ns act to pre command period tras 60 120000 ns pre to act command period trp 30 ? ns delay time act to read/write command t rcd 30 ? ns act (one) to act (another) command period t rrd 20 ? ns data-in to pre command period tdpl 20 ? ns data-in to act (ref) command period (auto precharge) (cl = 2) tdal2 2clk + 30 ? ns (cl = 3) tdal3 2clk + 30 ? ns mode register set cycle time trsc 2 ? clk transition time tt 1 30 ns refresh time (4,096 refresh cycles) tref 64 ? ms
edl1216casa data sheet e0195e30 (ver. 3.0) 9 pin function clk (input pin) clk is the master clock input. other inputs signals are referenced to the clk rising edge. cke (input pins) cke determine validity of the next clk (clock). if cke is high, the next clk rising edge is valid; otherwise it is invalid. if the clk rising edge is invalid, the internal clock is not issued and the mobile ram suspends operation. when the mobile ram is not in burst mode and cke is negated, the device enters power down mode. during power down mode, cke must remain low. /cs (input pins) /cs low starts the command input cycle. when /cs is high, commands are ignored but operations continue. /ras, /cas, and /we (input pins) /ras, /cas and /we have the same symbols on conventional dram but different functions. for details, refer to the command table. a0 to a11 (input pins) row address is determined by a0 to a11 at the clk (clock) rising edge in the active command cycle. it does not depend on the bit organization. column address is determined by a0 to 8 at the clk rising edge in the read or write command cycle. a10 defines the precharge mode. when a10 is high in the precharge command cycle, all banks are precharged; when a10 is low, only the bank selected by ba0 and ba1 is precharged. when a10 is high in read or write command cycle, the precharge starts automatically after the burst access. ba0 and ba1 (input pin) ba0 and ba1 are bank select signal. (see bank select signal table) [bank select signal table] ba0 ba1 bank a l l bank b h l bank c l h bank d h h remark: h: vih. l: vil. : vih or vil udqm and ldqm (input pins) udqm and ldqm control upper byte and lower byte i/o buffers, respectively. in read mode, dqm controls the output buffers like a conventional /oe pin. dqm high and dqm low turn the output buffers off and on, respectively. the dqm latency for the read is two clocks. in write mode, dqm controls the word mask. input data is written to the memory cell if dqm is low but not if dqm is high. the dqm latency for the write is zero. dq0 to dq15 (input/output pins) dq pins have the same function as i/o pins on a conventional dram. vdd, vss, vddq, vssq (power supply) vdd and vss are power supply pins for internal circuits. vddq and vssq are power supply pins for the output buffers.
edl1216casa data sheet e0195e30 (ver. 3.0) 10 command operation extended mode register set command (/cs, /ras, /cas, /we, ba0 = low, ba1 = high) the mobile ram has an extended mode register that defines low power functions. in this command, a0 through a11 are the data input pins. after power on, the extended mode register set command must be executed to fix low power functions. the extended mode register can be set only when all banks are in idle state. during trsc following this command, the mobile ram can not accept any other commands. c+ ch=< c]=< ch< hz+ h;z = =8a x=a x=8 extended mode register set command mode register set command (/cs, /ras, /cas, /we, ba0, ba1 = low) the mobile ram has a mode register that defines how the device operates. in this command, a0 through a11 are the data input pins. after power on, the mode register set command must be executed to initialize the device. the mode register can be set only when all banks are in idle state. during trsc following this command, the mobile ram cannot accept any other commands. c+ ch=< c]=< ch< hz+ h;z = =8a x=a x=8 mode register set command activate command (/cs, /ras = low, /cas, /we = high) the mobile ram has four banks, each with 4,096 rows. this command activates the bank selected by ba0 and ba1 and a row address selected by a0 through a11. this command corresponds to a conventional dram's /ras falling. c+ ch=< c]=< ch< hz+ h;z = =8a x=a-kx=8 ] ] activate command
edl1216casa data sheet e0195e30 (ver. 3.0) 11 precharge command (/cs, /ras, /we = low, /cas = high) this command begins precharge operation of the bank selected by ba0 and ba1. when a10 is high, all banks are precharged, regardless of ba0 and ba1. when a10 is low, only the bank selected by ba0 and ba1 is precharged. after this command, the mobile ram cant accept the activate command to the precharging bank during trp (precharge to activate command period). this command corresponds to a conventional drams /ras rising. c+ ch=< c]=< ch< hz+ h;z = =8a x=a-kx=8 mky precharge command write command (/cs, /cas, /we = low, /ras = high) this command sets the burst start address given by the column address to begin the burst write operation. the first write data in burst mode can input with this command with subsequent data on following clocks. c+ ch=< c]=< ch< hz+ h;z = =8a x=a-kx=8 h6 write command read command (/cs, /cas = low, /ras, /we = high) read data is available after /cas latency requirements have been met. this command sets the burst start address given by the column address. c+ ch=< c]=< ch< hz+ h;z = =8a x=a-kx=8 h6 read command
edl1216casa data sheet e0195e30 (ver. 3.0) 12 auto refresh command (/cs, /ras, /cas = low, /we, cke = high) this command is a request to begin the auto refresh operation. the refresh address is generated internally. before executing auto refresh, all banks must be precharged. after this cycle, all banks will be in the idle (precharged) state and ready for a row activate command. during trc1 period (from refresh command to refresh or activate command), the mobile ram cannot accept any other command = =8a x=a-kx=8 c+ ch=< c]=< ch< hz+ h;z auto refresh command self refresh entry command (/cs, /ras, /cas, cke = low, /we = high) after the command execution, self refresh operation continues while cke remains low. when cke goes high, the mobile ram exits the self refresh mode. during self refresh mode, refresh interval and refresh operation are performed internally, so there is no need for external control. before executing self refresh, all banks must be precharged. c+ ch=< c]=< ch< hz+ h;z = =8a x=a-kx=8 self refresh entry command power down entry command (/cs, cke = low, /ras, /cas, /we = high) after the command execution, power down mode continues while cke remains low. when cke goes high, the mobile ram exits the power down mode. before executing power down, all banks must be precharged. c+ ch=< c]=< ch< hz+ h;z = =8a x=a-kx=8 power down entry command
edl1216casa data sheet e0195e30 (ver. 3.0) 13 deep power down entry command( /cs, cke, /we = low, /ras, /cas = high) after the command execution, deep power down mode continues while cke remains low. when cke goes high, the mobile ram exits the deep power down mode. before executing deep power down, all banks must be precharged. c+ ch=< c]=< ch< hz+ h;z = =8a x=a-kx=8 deep power down entry command burst stop command (/cs = /we = low, /ras, /cas = high) this command can stop the current burst operation. c+ ch=< c]=< ch< hz+ h;z = =8a x=a-kx=8 burst stop command no operation (/cs = low, /ras, /cas, /we = high) this command is not an execution command. no operations begin or terminate by this command. c+ ch=< c]=< ch< hz+ h;z = =8a x=a-kx=8 no operation
edl1216casa data sheet e0195e30 (ver. 3.0) 14 truth table command truth table cke a11, function symbol n C 1 n /cs /ras /cas /we ba1 ba0 a10 a9 - a0 device deselect desl h h no operation nop h l h h h burst stop bst h h l h h l read read h l h l h v v l v read with auto precharge reada h l h l h v v h v write writ h l h l l v v l v write with auto precharge writa h l h l l v v h v bank activate act h l l h h v v v v precharge select bank pre h l l h l v v l precharge all banks pall h l l h l h mode register set mrs h l l l l l l l v extended mode register set emrs h l l l l h l l v remark: h: vih. l: vil. : vih or vil, v = valid data dqm truth table cke dqm function symbol n C 1 n u l data write / output enable enb h l l data mask / output disable mask h h h upper byte write enable / output enable enbu h l lower byte write enable / output enable enbl h l upper byte write inhibit / output disable masku h h lower byte write inhibit / output disable maskl h h remark: h: vih. l: vil. : vih or vil cke truth table cke current state function symbol n C 1 n /cs /ras /cas /we address activating clock suspend mode entry h l any clock suspend mode l l clock suspend clock suspend mode exit l h idle auto refresh command ref h h l l l h idle self refresh entry self h l l l l h idle power down entry pd h l l h h h h l h idle deep power down entry dpd h l l h h l self refresh self refresh exit l h l h h h l h h power down power down exit l h l h h h l h h deep power down deep power down exit l h remark: h: vih. l: vil. : vih or vil
edl1216casa data sheet e0195e30 (ver. 3.0) 15 function truth table current state /cs /ras /cas /we address command action notes idle h desl nop l h h h nop nop l h h l bst nop l h l h ba, ca, a10 read/reada illegal 2 l h l l ba, ca, a10 writ/ writa illegal 2 l l h h ba, ra act row activating l l h l ba, a10 pre/pall nop l l l h ref auto refresh l l l l oc, ba1= l mrs mode register set l l l l oc, ba1= h emrs extended mode register set row active h desl nop l h h h nop nop l h h l bst nop l h l h ba, ca, a10 read/reada begin read 3 l h l l ba, ca, a10 writ/ writa begin write 3 l l h h ba, ra act illegal 2 l l h l ba, a10 pre/pall precharge/precharge all banks 4 l l l h ref illegal l l l l oc, ba mrs/emrs illegal read h desl continue burst to end row active l h h h nop continue burst to end row active l h h l bst burst stop row active l h l h ba, ca, a10 read/reada terminate burst, begin new read 5 l h l l ba, ca, a10 writ/writa terminate burst, begin write 5, 6 l l h h ba, ra act illegal 2 l l h l ba, a10 pre/pall terminate burst precharging l l l h ref illegal l l l l oc, ba mrs/emrs illegal write h desl continue burst to end write recovering l h h h nop continue burst to end write recovering l h h l bst burst stop row active l h l h ba, ca, a10 read/reada terminate burst, start read : determine ap 5, 6 l h l l ba, ca, a10 writ/writa terminate burst, new write : determine ap 5 l l h h ba, ra act illegal 2 l l h l ba, a10 pre/pall terminate burst precharging 7 l l l h ref illegal l l l l oc, ba mrs/emrs illegal
edl1216casa data sheet e0195e30 (ver. 3.0) 16 current state /cs /ras /cas /we address command action notes read with auto h desl continue burst to end precharging precharge l h h h nop continue burst to end precharging l h h l bst illegal l h l h ba, ca, a10 read/reada illegal 2 l h l l ba, ca, a10 writ/ writa illegal 2 l l h h ba, ra act illegal 2 l l h l ba, a10 pre/pall illegal 2 l l l h ref illegal l l l l oc, ba mrs/emrs illegal write with auto precharge h desl continue burst to end write recovering with auto precharge l h h h nop continue burst to end write recovering with auto precharge l h h l bst illegal l h l h ba, ca, a10 read/reada illegal 2 l h l l ba, ca, a10 writ/ writa illegal 2 l l h h ba, ra act illegal 2 l l h l ba, a10 pre/pall illegal 2 l l l h ref illegal l l l l oc, ba mrs/emrs illegal precharging h desl nop enter idle after trp l h h h nop nop enter idle after trp l h h l bst illegal l h l h ba, ca, a10 read/reada illegal 2 l h l l ba, ca, a10 writ/writa illegal 2 l l h h ba, ra act illegal 2 l l h l ba, a10 pre/pall nop enter idle after trp l l l h ref illegal l l l l oc, ba mrs/emrs illegal row activating h desl nop enter bank active after trcd l h h h nop nop enter bank active after trcd l h h l bst illegal l h l h ba, ca, a10 read/reada illegal 2 l h l l ba, ca, a10 writ/writa illegal 2 l l h h ba, ra act illegal 2, 8 l l h l ba, a10 pre/pall illegal 2 l l l h ref illegal l l l l oc, ba mrs/emrs illegal
edl1216casa data sheet e0195e30 (ver. 3.0) 17 current state /cs /ras /cas /we address command action notes write recovering h desl nop enter row active after tdpl l h h h nop nop enter row active after tdpl l h h l bst nop enter row active after tdpl l h l h ba, ca, a10 read/reada begin read 6 l h l l ba, ca, a10 writ/ writa begin new write l l h h ba, ra act illegal 2 l l h l ba, a10 pre/pall illegal 2 l l l h ref illegal l l l l oc, ba mrs/emrs illegal write recovering h desl nop enter precharge after tdpl with auto l h h h nop nop enter precharge after tdpl precharge l h h l bst nop enter row active after tdpl l h l h ba, ca, a10 read/reada illegal l h l l ba, ca, a10 writ/writa illegal 2, 6 l l h h ba, ra act illegal 2 l l h l ba, a10 pre/pall illegal 2 l l l h ref illegal l l l l oc, ba mrs/emrs illegal refresh h desl nop enter idle after trc1 l h h h nop nop enter idle after trc1 l h h l bst nop enter idle after trc1 l h l h ba, ca, a10 read/reada illegal l h l l ba, ca, a10 writ/writa illegal l l h h ba, ra act illegal l l h l ba, a10 pre/pall illegal l l l h ref illegal l l l l oc, ba mrs/emrs illegal mode register h desl nop enter idle after trsc accessing l h h h nop nop enter idle after trsc l h h l bst nop enter idle after trsc l h l h ba, ca, a10 read/reada illegal l h l l ba, ca, a10 writ/writa illegal l l h h ba, ra act illegal l l h l ba, a10 pre/pall illegal l l l h ref illegal l l l l oc, ba mrs/emrs illegal
edl1216casa data sheet e0195e30 (ver. 3.0) 18 current state /cs /ras /cas /we address command action notes extended mode h desl nop enter idle after trsc register l h h h nop nop enter idle after trsc accessing l h h l bst nop enter idle after trsc l h l h ba, ca, a10 read/reada illegal l h l l ba, ca, a10 writ/writa illegal l l h h ba, ra act illegal l l h l ba, a10 pre/pall illegal l l l h ref illegal l l l l oc, ba0,ba1 mrs/emrs illegal remark: h: vih. l: vil. : vih or vil, v = valid data ba: bank address, ca: column address, ra: row address, oc: op-code notes: 1. all entries assume that cke is active (cke n-1 =cke n =h). 2. illegal to bank in specified states; function may be legal in the bank indicated by bank address (ba), depending on the state of that bank. 3. illegal if trcd is not satisfied. 4. illegal if tras is not satisfied. 5. must satisfy burst interrupt condition. 6. must satisfy bus contention, bus turn around, and/or write recovery requirements. 7. must mask preceding data which don't satisfy tdpl. 8. illegal if trrd is not satisfied.
edl1216casa data sheet e0195e30 (ver. 3.0) 19 simplified state diagram 4g 4g 4g 4g 4g 4g 4g 4g qp g p qp 3 3 gphpv gphpv q4 g 4g 4g g gp -g g 43phqv q4g - q - g gq- gq-q gq- g- gq-q g- g gq g g- gq g- g qp pp 4g 4g p - - -- --p
edl1216casa data sheet e0195e30 (ver. 3.0) 20 initialization the synchronous dram is initialized in the power-on sequence according to the following. (1) to stabilize internal circuits, when power is applied, a 200 s or longer pause must precede any signal toggling. (2) after the pause, all banks must be precharged using the precharge command (the precharge all banks command is convenient). (3) once the precharge is completed and the minimum trp is satisfied, two or more auto refresh must be performed. (4) both the mode register and the extended mode register must be programmed. after the mode register set cycle or the extended mode register set cycle, trsc (2 clk minimum) pause must be satisfied. remarks: 1 the sequence of auto refresh, mode register programming and extended mode register programming above may be transposed. 2 cke and dqm must be held high until the precharge command is issued to ensure data-bus high-z. programming mode registers the mode register and extended mode register are programmed by the mode register set command and extended mode register command, respectively using address bits a11 through a0, ba0 and ba1 as data inputs. the registers retain data until they are re-programmed, or the device enters into the deep power down or the device loses power. mode register the mode register has three fields; options : a11 through a7 /cas latency : a6 through a4 wrap type : a3 burst length : a2 through a0 following mode register programming, no command can be issued before at least 2 clk have elapsed. /cas latency /cas latency is the most critical of the parameters being set. it tells the device how many clocks must elapse before the data will be available. the value is determi ned by the frequency of the clock and the speed grade of the device. burst length burst length is the number of words that will be output or input in a read or write cycle. after a read burst is completed, the output bus will become high-z. the burst length is programmable as 1, 2, 4, 8 or full page. wrap type (burst sequence) the wrap type specifies the order in which the burst data will be addressed. this order is programmable as either sequential or interleave. the method chosen will depend on the type of cpu in the system. some microprocessor cache systems are optimized for sequential addressing and others for interleaved addressing. burst length sequence shows the addressing sequence for each burst length using them. both sequences support bursts of 1, 2, 4 and 8. additionally, sequence supports the full page length.
edl1216casa data sheet e0195e30 (ver. 3.0) 21 extended mode register the extended mode register has four fields; options : a11 through a7 drive strength : a6 through a5 temperature compensated self refresh : a4 through a3 partial array self refresh : a2 through a0 following extended mode register programming, no command can be issued before at least 2 clk have elapsed. drive strength driving capability of data output drivers. temperature compensated self refresh programmable refresh rate for self refresh mode to allow the system to control power as a function of temperature. partial array self refresh memory array size to be refreshed during self refresh operation is programmable in order to reduce power. data outside the defined area will not be retained during self refresh.
edl1216casa data sheet e0195e30 (ver. 3.0) 22 mode register definition p[p, , v z 3 + + + + + pp p[p+ , v z p 3v=+ +++ ++, +,+ +,, ,++ ,+, ,,+ ,,, 3p + , p q+ q, qv qq q q0 qh q qz qk q,+ q,, + + remark r : reserved ltmode pasr tcsr ds 0 0 0 0 0 extended mode register set refresh array all banks bank a & bank b (ba1=0) bank a (ba0=ba1=0) r r 1/2 of bank a (ra11=0) 1/4 of bank a (ra11=ra10=0) r bits2-0 000 001 010 011 100 101 110 111 partial array self refresh max temperature 70
edl1216casa data sheet e0195e30 (ver. 3.0) 23 burst length and sequence [burst of two] starting address (column address a0, binary) sequential addressing sequence (decimal) interleave addressing sequence (decimal) 0 0, 1 0, 1 1 1, 0 1, 0 [burst of four] starting address (column address a1 ? a0, binary) sequential addressing sequence (decimal) interleave addressing sequence (decimal) 00 0, 1, 2, 3 0, 1, 2, 3 01 1, 2, 3, 0 1, 0, 3, 2 10 2, 3, 0, 1 2, 3, 0, 1 11 3, 0, 1, 2 3, 2, 1, 0 [burst of eight] starting address (column address a2 ? a0, binary) sequential addressing sequence (decimal) interleave addressing sequence (decimal) 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 full page burst is an extension of the above tables of sequential addressing, with the length being 512.
edl1216casa data sheet e0195e30 (ver. 3.0) 24 address bits of bank-select and precharge =88 =8a =f =f =v =k =7 =4 =z =g =8 =a ] m=ky =88 =8a =f =f =v =k =7 =4 =z =g =8 =a mky disables auto-precharge (end of burst) 0 enables auto-precharge (end of burst) 1 a11 a10 a9 a8 a7 a6 a4 a5 a3 a2 a1 a0 col. (/cas strobes) x : don?t care select bank a ?activate? command 0 select bank b ?activate? command 0 1 1 0 1 0 1 ba1 ba0 ba1 ba0 ba1 ba0 result select bank c ?activate? command select bank d ?activate? command enables read/write commands for bank a 0 enables read/write commands for bank b 0 1 1 0 1 0 1 result enables read/write commands for bank c enables read/write commands for bank d result precharge bank a precharge bank b precharge bank c precharge bank d precharge all banks a10 0 0 0 0 1 0 0 1 1 x 0 1 0 1 x ba1 ba0 ba1 ba0 ba1 ba0
edl1216casa data sheet e0195e30 (ver. 3.0) 25 operation of the mobile ram precharge the precharge command can be issued anytime after tras min. is satisfied. soon after the precharge command is issued, precharge operation performed and the synchronous dram enters the idle state after trp is satisfied. the parameter trp is the time required to perform the precharge. the earliest timing in a read cycle that a precharge command can be issued without losing any data in the burst is as follows. >a >8 >g >z >7 >4 >k >v xkw7 ]+=C ]+=C [8 [g [z [7 ]+ t [8 [g [z [7 ]+ t m ]=< kkky h;z h ch=f precharge in order to write all data to the memory cell correctly, the asynchronous parameter tdpl must be satisfied. the tdpl (min.) specification defines the earliest time that a precharge command can be issued. minimum number of clocks is calculated by dividing tdpl (min.) with clock cycle time. in summary, the precharge command can be issued relative to reference clock that indicates the last data word is valid. in the following table, minus means clocks before the reference; plus means time after the reference. /cas latency read write 2 -1 +tdpl(min.) 3 -2 +tdpl(min.)
edl1216casa data sheet e0195e30 (ver. 3.0) 26 auto precharge during a read or write command cycle, a10 controls whether auto precharge is selected. a10 high in the read or write command (read with auto precharge command or write with auto precharge command), auto precharge is selected and begins automatically. the tras must be satisfied with a read with auto precharge or a write with auto precharge operation. in addition, the next activate command to the bank being precharged cannot be executed until the precharge cycle ends. in read cycle, once auto precharge has started, an activate command to the bank can be issued after trp has been satisfied. in write cycle, the tdal must be satisfied to issue the next activate command to the bank being precharged. the timing that begins the auto precharge cycle depends on whether read or write cycle. read with auto precharge during a read cycle, the auto precharge begins one clock earlier (/cas latency of 2) or two clocks earlier (/cas latency of 3) the last data word output. [x8 [xg [xz [x7 =kk ]+=C=kx t [x8 [xg [xz [x7 =kk ]+=C=kx t C[ h C[ h ch=a >g >8 >z >7 >4 >k >v >f xkkwk7 m ]=< kkky >f read with auto precharge remark: reada means read with auto precharge write with auto precharge during a write cycle, the auto precharge starts at the timing that is equal to the value of the tdpl (min.) after the last data word input to the device. Cx8 Cxg Cxz Cx7 =kk ]>=kx t C[ h h;z >a >g >8 >z >7 >4 >k >v >f xkkwk7 m ]=< kkky C;m'?6y write with auto precharge remark: writa means write with auto precharge
edl1216casa data sheet e0195e30 (ver. 3.0) 27 read / write command interval read to read command interval during a read cycle, when new read command is issued, it will be effective after /cas latency, even if the previous read operation does not completed. read will be interrupted by another read. the interval between the commands is 1 cycle minimum. each read command can be issued in every clock without any restriction. [x8 [xg [xz [x7 t ]+=Ck= C[ h h;z >a >g >8 >z >7 >4 >k >v >f xkkwk7-kch=f read to read command interval write to write command interval during a write cycle, when a new write command is issued, the previous burst will terminate and the new burst will begin with a new write command. write will be interrupted by another write. the interval between the commands is minimum 1 cycle. each write command can be issued in every clock without any restriction. Cx8 Cxg Cxz Cx7 t ]>+k= C[ h h;z >a >g >8 >z >7 >4 >k >v >f xkkwk7 ]>+kx C=8 8 write to write command interval
edl1216casa data sheet e0195e30 (ver. 3.0) 28 write to read command interval write command and read command interval is also 1 cycle. only the write data before read command will be written. the data bus must be high-z at least one cycle prior to the first dout. [x8 [xg [xz [x7 ]>+k= t [x8 [xg [xz [x7 ]>+k= t C[ h C[ h ch=a >g >8 >z >7 >4 >k >v >f xkkwk7 C=8 C=8 ]+=Ckx ]+=Ckx write to read command interval
edl1216casa data sheet e0195e30 (ver. 3.0) 29 read to write command interval during a read cycle, read can be interrupted by write. the read and write command interval is 1 cycle minimum. there is a restriction to avoid data conflict. the data bus must be high-z using dqm before write. C8 Cg Cz C7 ]+=Ck C[ h h;z >a >g >8 >z >7 >4 >k >v >f xkkwk7 ]>+ C[' t 8 read to write command interval 1 read can be interrupted by write. dqm must be high at least 3 clocks prior to the write command. h;z >a >g >8 >z >7 >4 >k >v >f xkkwkf >f [8 [g [z ]+=C C[ h C8 Cg Cz ]>+ C[' tk [8 [g ]+=C C[ h C8 Cg Cz ]>+ C[' tk ch= edl1216casa data sheet e0195e30 (ver. 3.0) 30 burst termination there are two methods to terminate a burst operation other than using a read or a write command. one is the burst stop command and the other is the precharge command. burst termination in read cycle during a read cycle, when the burst stop command is issued, the burst read data are terminated and the data bus goes to high-z after the /cas latency from the burst stop command. ]+=C h h;z >a >g >8 >z >7 >4 >k >v xkkwk [8 [g [z C[ ch= burst termination in read cycle remark: bst: burst stop command burst termination in write cycle during a write cycle, when the burst stop command is issued, the burst write data are terminated and data bus goes to high-z at the same clock with the burst stop command. Cg Cz C7 ]>+ C[ h h;z >a >g >8 >z >7 >4 >k >v xkkwk x<> t C8 burst termination in write cycle remark: bst: burst stop command
edl1216casa data sheet e0195e30 (ver. 3.0) 31 precharge termination in read cycle during a read cycle, the burst read operation is terminated by a precharge command. when the precharge command is issued, the burst read operation is terminated and precharge starts. the same bank can be activated again after trp from the precharge command. to issue a precharge command, tras must be satisfied. when /cas latency is 2, the read data will remain valid until one clock after the precharge command. ]+=C h;z >a >g >8 >z >7 >4 >k >v xkkwk-kch= ] ]+ t m ]=< kkky precharge termination in read cycle (cl = 2) when /cas latency is 3, the read data will remain valid until two clocks after the precharge command. ]+=C h;z >a >g >8 >z >7 >4 >k >v xkkwk-kch= ] ]+ t >f [7 m ]=< kkky precharge termination in read cycle (cl = 3)
edl1216casa data sheet e0195e30 (ver. 3.0) 32 precharge termination in write cycle during a write cycle, the burst write operation is terminated by a precharge command. when the precharge command is issued, the burst write operation is terminated and precharge starts. the same bank can be activated again after trp from the precharge command. to issue a precharge command, tras must be satisfied. the write data written prior to the precharge command will be correctly stored. however, invalid data may be written at the same clock as the precharge command. to prevent this from happening, dqm must be high at the same clock as the precharge command. this will mask the invalid data. ]>+ h;z >a >g >8 >z >7 >4 >k >v xkkwk-kch= C[' ] ]+ t C4 >f C7 m ]=< kkky precharge termination in write cycle
edl1216casa data sheet e0195e30 (ver. 3.0) 33 timing waveforms ac parameters for read timing with manual precharge t oh t lz t ac t oh t ac t ac t oh t oh t ac t hz t ras t rc ba0 t ckh t rp t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 clk cke /cs /ras /cas /we ba1 a10 add dqm dq t rcd t cks t ch t cl t ck t cms t cmh t as t ah l hi-z activate command for bank a precharge command for bank a read command for bank a activate command for bank a [burst length = 4, /cas latency = 3]
edl1216casa data sheet e0195e30 (ver. 3.0) 34 ac parameters for read timing with auto precharge 4 t oh t lz t ac t oh t ac t ac t oh t oh t ac t hz t ras t rrd t rc ba0 t ckh t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 clk cke /cs /ras /cas /we ba1 a10 add dqm dq t rcd t ch t cl t ck t cms t cmh t as t ah l hi-z auto precharge start for bank c activate command for bank c activate command for bank d read with auto precharge command for bank c activate command for bank c [burst length = 4, /cas latency = 3]
edl1216casa data sheet e0195e30 (ver. 3.0) 35 ac parameters for write timing t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke ba0 a10 add dqm dq hi-z t as t ah t ds t dh t rcd t dal t rc t rrd t rcd t ras t rc t dpl t rp t ckh t cms t cmh t cks /cs /ras /cas /we ba1 auto precharge start for bank c l activate command for bank c activate command for bank b write command for bank b activate command for bank b write with auto precharge command for bank c precharge command for bank b activate command for bank c [burst length = 4]
edl1216casa data sheet e0195e30 (ver. 3.0) 36 mode register set 4 4g 54 5q 54q 5g 3q+ q,+ q-- - - ba1 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 hi-z address key t rp precharge all banks command mode register set command activate command is valid h t rsc 2 clk (min.)
edl1216casa data sheet e0195e30 (ver. 3.0) 37 extended mode register set 4 4g 54 5q 54q 5g 3q+ q,+ q-- - - ba1 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 hi-z address key t rp precharge all banks command extended mode register set command activate command is valid h t rsc 2 clk (min.) power on sequence 4 4g 54 5q 54q 5g 3q, q,+ q-- - - hi-z t rsc t rsc address key address key t rp high level is necessary 2 refresh cycles are necessary t rc1 t rc1 precharge all banks command is necessary mode register set command is necessary extended mode register set command is necessary cbr (auto) refresh command is necessary activate command cbr (auto) refresh command is necessary ba0 high level is necessary clock cycle is necessary
edl1216casa data sheet e0195e30 (ver. 3.0) 38 /cs function only /cs signal needs to be issued at minimum rate 4 4g 54 5q 54q 5g 3q, q,+ q-- - - + , v q 0 h z k ,+ ,, ,v ,q , ,0 , ,h ,z ,k v+ v, = 3q+ q q, qv qq q -q, -qv -qq -q q 4 p3pq 4 p3pq 4 p3pq 4 p3pq q 4q 4q [burst length = 4, /cas latency = 3]
edl1216casa data sheet e0195e30 (ver. 3.0) 39 clock suspension during burst read 4 4g 54 5q 54q 5g 3q, q,+ q-- - - t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 qaa1 qaa2 qaa3 qaa4 caa ba0 l hi-z raa raa activate command for bank a read command for bank a 1-clock suspended 2-clock suspended 3-clock suspended hi-z (turn off) at the end of burst [burst length = 4, /cas latency = 3] h;z hz+ ch< c]=< ch=< c+ x=8 =8a =CC C[' C[ t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 qaa1 qaa2 qaa3 qaa4 caa ba0 l hi-z raa raa activate command for bank a read command for bank a 1-clock suspended 2-clock suspended 3-clock suspended hi-z (turn off) at the end of burst [burst length = 4, /cas latency = 2]
edl1216casa data sheet e0195e30 (ver. 3.0) 40 clock suspension during burst write 4 4g 54 5q 54q 5g 3q, q,+ q-- - - t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 caa ba0 l hi-z raa raa daa1 daa2 daa3 daa4 activate command for bank a 1-clock suspended 2-clock suspended 3-clock suspended write command for bank a
edl1216casa data sheet e0195e30 (ver. 3.0) 41 power down mode and clock mask 4 4g 54 5q 54q 5g 3q, q,+ q-- - - t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 qaa3 caa l hi-z raa ba0 t cksp t cksp qaa1 qaa2 valid activate command for bank a power down mode entry active standby power down mode exit read command for bank a clock mask start clock mask end power down mode entry precharge command for bank a precharge standby power down mode exit qaa4 raa [burst length = 4, /cas latency = 3] h;z hz+ ch< c]=< ch=< c+ x=8 =8a =CC C[' C[ t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 qaa3 caa l hi-z raa ba0 t cksp t cksp qaa1 qaa2 valid activate command for bank a power down mode entry active standby power down mode exit read command for bank a clock mask start clock mask end power down mode entry precharge command for bank a precharge standby power down mode exit qaa4 raa [burst length = 4, /cas latency = 2]
edl1216casa data sheet e0195e30 (ver. 3.0) 42 auto refresh h;z hz+ ch< c]=< ch=< c+ x=8 =8a =CC C[' C[ >a >8 >g >z >7 >4 >k > > k i k 8> k i k g> k i k z> k i k 7> k i k 4> k i k k>> k i k 8> k i k g> k i k z> k i k 7> k i k 4> k i k k> k i k v ba0 l hi-z t rp h t rc1 t rc1 q1 precharge command (if necessary) cbr (auto) refresh cbr (auto) refresh activate command read command
edl1216casa data sheet e0195e30 (ver. 3.0) 43 self refresh (entry and exit) 4 4g 54 5q 54q 5g 3q, q,+ q-- - - t0 t1 t2 t3 t4 tn tn + 1tn + 2tmtm + 1tktk + 1tk + 2tk + 3tk + 4 t rp t rc1 t rc1 ba0 precharge command (if necessary) self refresh entry self refresh exit next clock enable self refresh entry (or activate command) activate command self refresh exit next clock enable l hi-z
edl1216casa data sheet e0195e30 (ver. 3.0) 44 deep power down entry 4 4g 54 5q 54q 5g 3q+ q,+ q-- - - ba1 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 hi-z t rp precharge all banks command deep power down entry l deep power down exit 4 4g 54 5q 54q 5g 3q, q,+ q-- - - hi-z t rsc t rsc address key address key t rp 200 high level is necessary 2 refresh cycles are necessary t rc1 t rc1 precharge all banks command is necessary deep power down exit command mode register set command is necessary extended mode register set command is necessary cbr (auto) refresh command is necessary activate command cbr (auto) refresh command is necessary ba0 high level is necessary clock cycle is necessary
edl1216casa data sheet e0195e30 (ver. 3.0) 45 random column read 4 4g 54 5q 54q 5g 3q, q,+ q-- - - 4 p3pq q 4 p3pq 4 p3pq 4 p3pq 4 p3pq q 4 p3pq 4 p3pq + , v q 0 h z k ,+ ,, ,v ,q , ,0 , ,h ,z ,k v+ v, qaa1 qaa2 qaa3 qaa4 qab1 qab2 qac1 qac2 qac3 qac4 h raa raa caa cac caa raa cab ba0 raa l hi-z [burst length = 4, /cas latency = 3] h;z hz+ ch< c]=< ch=< c+ x=8 =8a =CC C[' C[ t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 qaa1 qaa2 qaa3 qaa4 qab1 qab2 qac1 qac2 qac3 qac4 qad1 qad2 qad3 h rad raa cad cac caa rad cab ba0 raa precharge command for bank a activate command for bank a read command for bank a read command for bank a read command for bank a activate command for bank a read command for bank a l hi-z [burst length = 4, /cas latency = 2]
edl1216casa data sheet e0195e30 (ver. 3.0) 46 random column write 4 4g 54 5q 54q 5g 3q, q,+ q-- - - t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l hi-z dda1 dda2 dda3 dda4 ddb1 ddb2 ddc1 ddc2 ddc3 ddc4 h rdd rda cdd cdc cda rdd cdb ba0 rda ddd1 activate command for bank d write command for bank d write command for bank d write command for bank d precharge command for bank d activate command for bank d write command for bank d ddd2 [burst length = 4]
edl1216casa data sheet e0195e30 (ver. 3.0) 47 random row read 4 4g 54 5q 54q 5g 3q+ q,+ q-- - - t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l hi-z qba1 qba2 qba3 qba4 qba5 qba6 qba7 qba8 qaa1 qaa2 qaa3 qaa4 qaa5 h rbb rba cbb caa cba rbb raa rba raa qaa6 qaa7 ba1 activate command for bank b read command for bank b activate command for bank a read command for bank a precharge command for bank b activate command for bank b read command for bank b precharge command for bank a [burst length = 8, /cas latency = 3] h;z hz+ ch< c]=< ch=< c+ x=8 =8a =CC C[' C[ t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l hi-z qda1 qda2 qda3 qda4 qda5 qda6 qda7 qda8 qba1 qba2 qba3 qba4 qba5 h rdb rda cdb cba cda rdb rba rda ba0 rba qba6 qba7 qba8 activate command for bank d read command for bank d activate command for bank b read command for bank b precharge command for bank d activate command for bank d read command for bank d [burst length = 8, /cas latency = 2]
edl1216casa data sheet e0195e30 (ver. 3.0) 48 random row write 4 4g 54 5q 54q 5g 3q, q,+ q-- - - t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 daa3 daa4 daa5 daa6 daa7 daa8 dda1 dda2 dda3 dda5 dda6 dda7 h raa cab cda rda raa rda dda8 dab1 dab2 rab daa1 daa2 ba0 caa rab activate command for bank a write command for bank a write command for bank d activate command for bank d precharge command for bank a activate command for bank a precharge command for bank d write command for bank a l hi-z dda4 [burst length = 8]
edl1216casa data sheet e0195e30 (ver. 3.0) 49 read and write 4 4g 54 5q 54q 5g 3q, q,+ q-- - - t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 qaa1 qaa2 qaa3 qaa4 dab1 dab2 qac1 qac2 h raa cac cab dab4 caa raa ba0 activate command for bank a read command for bank a write command for bank a 0-clock latency read command for bank a word masking write latency = 0 l hi-z hi-z at the end of wrap function 2-clock latency [burst length = 4, /cas latency = 3] h;z hz+ ch< c]=< ch=< c+ x=8 =8a =CC C[' C[ = h kxk= ] h kxk= h kxk= athk; gthk; ] h kxk= t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 qaa1 qaa2 qaa3 qaa4 dab1 dab2 qac1 qac2 qac4 h raa cac cab dab4 ba0 caa write latency = 0 raa word masking l hi-z hi-z at the end of wrap function [burst length = 4, /cas latency = 2]
edl1216casa data sheet e0195e30 (ver. 3.0) 50 interleaved column read cycle 4 4g 54 5q 54q 5g 3q, q,+ q-- - - t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l hi-z aa1 aa2 aa3 aa4 da1 da2 dc1 dc2 ab3 ab4 h ab1 ab2 db1 db2 raa rda ba0 raa cab cdc rda cda caa activate command for bank a activate command for bank d read command for bank d read command for bank d read command for bank d read command for bank a precharge command for bank d precharge command for bank a read command for bank a cdb [burst length = 4, /cas latency = 3] h;z hz+ ch< c]=< ch=< c+ x=8 =8a =CC C[' C[ t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l hi-z aa1 aa2 aa3 aa4 da1 da2 dc1 dc2 dd1 dd2 dd3 dd4 h raa rda ab1 ab2 db1 db2 ba0 raa rda caa cda cdb cdc cab cdd activate command for bank a activate command for bank d read command for bank d read command for bank d read command for bank d read command for bank a read command for bank d precharge command for bank a precharge command for bank d read command for bank a [burst length = 4, /cas latency = 2]
edl1216casa data sheet e0195e30 (ver. 3.0) 51 interleaved column write cycle 4 4g 54 5q 54q 5g 3q+ q,+ q-- - - t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l hi-z aa1 aa2 aa3 aa4 ba1 ba2 bc1 bc2 bd1 bd2 h ab1 ab2 bb1 bb2 raa rba raa cab cbc rba cba cbb caa cbd bd3 bd4 activate command for bank a write command for bank a activate command for bank b write command for bank b write command for bank a precharge command for bank a precharge command for bank b write command for bank b write command for bank b write command for bank b ba1 [burst length = 4]
edl1216casa data sheet e0195e30 (ver. 3.0) 52 auto precharge after read burst 4 4g 54 5q 54q 5g 3q+ q,+ q-- - - t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l h rdb raa raa cab caa rdb cda rda cdb hi-z ba1 rda activate command for bank a activate command for bank d read command for bank a read with auto precharge command for bank d read with auto precharge command for bank a read with auto precharge command for bank d auto precharge start for bank d activate command for bank d auto precharge start for bank a [burst length = 4, /cas latency = 3] h;z hz+ ch< c]=< ch=< c+ x=a =8a =CC C[' C[ t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l h ba1 rdb rac rda raa raa cab caa rdb cda rda cac cdb rac hi-z activate command for bank a activate command for bank d read command for bank a read with auto precharge command for bank d read with auto precharge command for bank a auto precharge start for bank d read with auto precharge command for bank d auto precharge start for bank a auto precharge start for bank d activate command for bank a read with auto precharge command for bank a activate command for bank d [burst length = 4, /cas latency = 2]
edl1216casa data sheet e0195e30 (ver. 3.0) 53 auto precharge after write burst 4 4g 54 5q 54q 5g 3q+ q,+ q-- - - t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l h rdb raa raa cab caa rdb cda rda cdb rda ba1 hi-z activate command for bank a write command for bank a activate command for bank d write with auto precharge command for bank d write with auto precharge command for bank a auto precharge start for bank d auto precharge start for bank a activate command for bank d write with auto precharge command for bank d [burst length = 4]
edl1216casa data sheet e0195e30 (ver. 3.0) 54 burst write operation 4 4g 54 5q 54q 5g 3q+ q,+ q-- - t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 udqm ba1 dq (lower) dq (upper) activate command for bank d read command for bank d read command for bank d upper byte not read lower byte not read lower byte not read lower byte not read lower byte not write upper byte not write lower byte not write [burst length = 4]
edl1216casa data sheet e0195e30 (ver. 3.0) 55 precharge termination 4 4g 54 5q 54q 5g 3q+ q,+ q-- - - t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l hi-z h ba1 raa rab caa raa rab cab daa1 daa2 daa3 qab1 qab2 qab3 qab4 hi-z activate command for bank a activate command for bank a write command for bank a pre termination of burst precharge command for bank a precharge command for bank a activate command for bank a read command for bank a pre termination of burst daa4 daa5 write masking rac rac t rcd t rp t ras t dpl t ras [burst length = 8, /cas latency = 3] h;z hz+ ch< c]=< ch=< c+ x=a =8a =CC C[' C[ t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l h ba1 hi-z raa rab caa raa rab cab daa1 daa2 daa3 daa4 daa5 qab1 qab2 qab3 qab4 qab5 activate command for bank a activate command for bank a write command for bank a pre termination of burst pre termination of burst precharge command for bank a activate command for bank a read command for bank a precharge command for bank a hi-z write masking rac rac t rcd t dpl t rp t ras t ras [burst length = 8, /cas latency = 2]
edl1216casa data sheet e0195e30 (ver. 3.0) 56 package drawing 54-ball fbga ( bga) solder ball: lead free (sn-ag-cu) f6a ??
edl1216casa data sheet e0195e30 (ver. 3.0) 57 recommended soldering conditions please consult with our sales offices for soldering conditions of the edl1216casa. type of surface mount device edl1216casa: 54-ball fbga ( bga) < lead free (sn-ag-cu) >
edl1216casa data sheet e0195e30 (ver. 3.0) 58 >+?k="=?<>k+kkkkkk k6k'k?kkkkkkkkkkk6 z <>=>=;=>?k*k' edl1216casa data sheet e0195e30 (ver. 3.0) 59 bga is a registered trademark of tessera, inc. 'a8+a8av kkkkkkkkkkkkkkkkkkkk kkk+k'-k6 +k'-k6kkkkkkkkkkkkk mkkkkk-k-kkkkykk+k'-k6kk kkkkkkkkkkkkkkkk6kk-k -kkk-kkkkk-kkkkkk kk+k'-k6kk6 Ckk-kkkkkkkkkkkk kkkkkkkk6k>kkk k-kkkkkkkkkwkkkkkk kkkkk6k+k'-k6kkkkkkk kkkkkkkkkkkk-kkk6 k +k'-k6kkkkkkkkkkkkkk6k -kkkkkk+k'wkkkkkkkk -k-kk-kk-k-k-kk-k kkkk-kkkkkkkkkkk kkkkkkkkkkkkkkkkk kk6 k Ckkkkkkkkkkkkkkkk +k'-k6-kkkk-kkkk-kkk -kkkkkk6k+k'-k6kkk kkkkkkkkkkkkkkk 6k+kkkkkk-kkkkk kkkkkkkkkkkkkt-kk kkkk+k'-k6kkkkkk-kkkk kkkkkkkk+k'-k6k6 k >kkkkkkkkkkkk6k>kkkk kkktk6 kkkkkkkkkkkkkkkk*k +kk*k>k;kk-kkkkkkkkk kkkkkkk6k=-kkkkckkk 6<6kkk-kkkwkkkkk-kkkk kkkkkkkkk6 kkckk-k-kkkkkk-kkkkkkk kkkk-kkkkkkkkkkkkk kkkkkk6 >kkkkkkkkkk6kxkkk-kkkkkk k6

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